1. Field of the Invention
This invention relates to a semiconductor process, and more particularly relates to a conductor removal process that is applied to a substrate having thereon a plurality of patterns and a blanket conductor layer covering the patterns and to a silicon removal process derived from the conductor removal process.
2. Description of the Related Art
In current integrated circuit (IC) process, chemical mechanical polishing (CMP) is the major technique to make global planarization. Almost any material formed on a wafer, such as polysilicon, silicon oxide or a metal, can be polished with a suitable polishing slurry. For example, polysilicon is conventionally polished with a polishing slurry based on a silica (SiO2) abrasive.
However, because native oxide is easily formed on poly-Si, a silica/ceria slurry is needed to polish native oxide before the silica slurry is used so that the polysilicon CMP process is complicated. Moreover, as the polysilicon is formed covering patterns of silicon oxide and has to be removed partially to expose the patterns, poly-Si recess or oxide loss easily occur during the over-polishing stage due to the lower oxide/poly-Si selectivity of silica slurry.
For example, FIG. 1 illustrates the result of a poly-Si CMP process using a silica/ceria slurry and a silica slurry on a polysilicon layer in a self-aligned gate fabricating process as described in U.S. Pat. Nos. 6,610,577 and 6,924,220.
Referring to FIG. 1, the substrate 100 includes a memory array area 102 and a peripheral area 104. Isolation patterns 110 of silicon oxide has been formed in the substrate 100 protrudent over the same, a gate dielectric layer 120 formed on the substrate 100 between the isolation patterns 110 and a polysilicon layer 130 formed on the substrate 100 covering the isolation patterns 110. After the native oxide is polished away with a silica/ceria slurry, a silica slurry is used to polish away a portion of the polysilicon layer 130 and thus expose the isolation patterns 110. The remaining polysilicon layer 130 includes gates 130a of MOS devices (not shown) in the memory array area 102 and gates 130b of those (not shown) in the peripheral area 104, as indicated by the dash lines in the figure.
However, since the oxide/polysilicon polishing selectivity of silica slurry is poor, recess easily occurs to the wider gates 130b in the peripheral area 104 during the over-polishing, as indicated by the curved dash line, so that the resistance of the gates 130b is not easy to control. Though forming protective oxide over portions of the polysilicon layer 130 to be polished to form the gates 130b can prevent recesses on the gates 130b, the process of forming and defining the protective oxide is quite time-consuming.